The present invention relates to a method and a device for determining a semiconductor low current (e.g., a bit line leak current in a semiconductor memory such as a flash memory).
In recent years, a non-volatile memory such as a flash memory and an EEPROM employs a large-capacity memory array configuration using miniaturized memory cells.
One of the problems that recent non-volatile memories are facing is the increase in the bit line leak current due to an increase in the memory array capacity. This is because of the increase in the number of memory cells per bit line, in addition to the increase in the leak current (bit line leak current) per memory cell, which is caused by the miniaturization process. An increase in the bit line leak current influences the memory cell read operation, thereby detracting from the precision of the memory cell threshold value control and thus deteriorating the reliability, e.g., the data holding property.
The write/erase operation for a non-volatile memory cell is controlled by repeatedly performing the operation of changing the threshold value of the memory cell by applying a write/erase bias and the threshold value determination, i.e., a verifying operation of determining the cell current. In a verifying operation, a bit line leak current causes the system to erroneously determine the cell current by the magnitude of the leak current, thereby leading to overwriting, undererasing, etc., thus preventing the system from normally controlling the threshold value of a memory cell.
In order to realize a high reliability of a memory, any bit line whose leak is determined to be greater than or equal to a predetermined value in a device test needs to be replaced by redundant replacement, or the device needs to be rejected as being a defective device. Conventional bit line leak current determination for leak currents on the order of μA used a sense amplifier, which is for use in the read operation.
Patent Document 1, identified below, describes the determination of the bit line leak current with a sense amplifier. Patent Document 2 describes a method for directly measuring a leak current, Patent Document 3 a method for measuring the threshold value of a cell, and Patent Document 4 a method for on-chip current measurement.
Patent Document 1: Japanese Laid-Open Patent Publication No. 6-251593
Patent Document 2: U.S. Pat. No. 6,201,747
Patent Document 3: U.S. Pat. No. 6,370,061
Patent Document 4: Laid-Open Patent Publication No. 2005-302809
However, the decrease in the cell current due to miniaturization of memory cells, the demand for improving the number of write cycles, the increase in the number of threshold values, etc., make it necessary to improve the precision of the threshold value control, and there is accordingly a demand for determining even lower currents, i.e., on the sub-μA level. In the conventional measurement of such low currents, bit lines are selectively drawn directly onto external pads and the currents are measured by a current measurement option of a test apparatus.
FIG. 20 shows a configuration of a conventional memory having a bit line leak current measurement function. A memory 100 includes a data storage section 102 for writing/reading data, a switch 2000 for connecting a selected bit line in the data storage section 102 to an external terminal 110 via a node 108 for measuring the current of the bit line, and a control circuit 104 for controlling the data storage section 102 and the switch 2000.
When determining a leak current of a bit line, memory cells in the data storage section 102 are controlled by the control circuit 104 to be unselected. The switch 2000 connects the node 108, to which a selected bit line is connected, to the external terminal 110. Then, the current value is measured by a current measurement option of a test apparatus connected to the external terminal 110.
FIG. 21 shows an exemplary circuit configuration of a main part of the memory 100 in a case where a virtual ground array (VGA) configuration, which is suitable for large-capacity memories, is applied to the data storage section 102.
A memory cell array 801 includes memory cells arranged in a matrix pattern, wherein gates of memory cells of the same row are connected together and to word lines WL0 and WL1, sources of memory cells of the same column are connected together and to source bit lines BL0 and BL2, which give a source potential, and drains of memory cells of the same column are connected together and to a drain bit line BL1, which give a drain potential.
Methods for reading out stored data from a memory cell include a drain read method of determining the current or level on the drain side of the memory cell, and a source read method of determining the current or level on the source side of the memory cell. The mainstream is the source read method, with which the influence of the memory cell leak current is-smaller and the power consumption can be suppressed smaller, and FIG. 21 shows an example of the source read method.
A column selection gate (D) 804 is a selection gate for selecting a drain bit line, to which the drain of the memory cell is connected, and gives a read voltage (about 1.3 V) according to the potential VBLR, via a bias transistor 808, to the drain bit line selected by the selection gate connected to a selection signal YGD1. A column selection gate (S) 802 is a selection gate for selecting a source bit line, to which the source of the memory cell is connected, and selectively connects the source bit line selected by the selection gates connected to selection signals YGS1 and YGS2 to the node 108, at which a sense amplifier 810, a reset transistor 806 and the switch 2000 are connected together.
FIG. 22 shows a timing waveform of the operation of reading out data stored in a memory cell. In the period until time t1 where the signal SEN is “H”, the transistor 806 is ON, and the potential VBL at the node 108 remains at the GND level. When the signal SEN transitions to the “L” level at time t1, the transistor 806 is turned OFF, and the node 108 is charged by the current of the selected memory cell. Where the selected memory cell is ON (i.e., it is an ON-cell), the potential of the node 108 increases as shown in (VBL_1). However, where the selected memory cell is OFF (i.e., it is an OFF-cell), the potential of the node 108 remains at the ground potential as shown in (VBL_2). A read reference current being about ½ the current of an ON memory cell flows from a circuit (not shown) to the reference node being the other input of the sense amplifier 810, thereby charging the reference node. Thus, the potential VREF of the reference node is a middle potential between (VBL_1) and (VBL_2), as shown in FIG. 22.
At time t2, when the potential difference between the potential VBL of the source node of the memory cell and the potential VREF of the reference node has increased sufficiently, the determination output Sout from the sense amplifier 810 is decided as being the read data from the memory cell, thus completing the read operation, after which the signal SEN is brought to the “H” level to discharge the node 108.
Where there is a leak current on the source bit line BL0 or BL2, to which the source of the memory cell is connected, the leak current is added to the memory cell current, and the potentials of (VBL_1) and (VBL_2) are increased. Then, the potential difference between the potential (VBL_2) where the selected memory cell is OFF and the potential (VREF) of the reference node decreases, thereby reducing the read margin.
Thus, during the product inspection stage of the production process, it is necessary to determine the leak current value of each bit line, and if there is a leak greater than or equal to a predetermined value, the bit line needs to be replaced by redundant replacement, or the device needs to be rejected as being a defective device.
Therefore, for the purpose of bit line leak current determination, the switch 2000 is provided, which connects the VBL node 108 to the external terminal 110. In the bit line leak determination, under control of the control circuit 104, the ground potential representing the “unselected state” is given to all word lines WL0 and WL1, and the column selection gate (D) 804 and the column selection gate (S) 802 select a drain bit line and a source bit line, respectively, whose leak is to be determined, thereby selecting a group of memory cells (a column of memory cells) whose leak is to be determined.
A read voltage of about 1.3 V is given to the selected drain bit line via the bias transistor 808 as in a read operation, and the node 108, to which the selected source bit line is output, is connected to the external terminal 110 via the switch 2000. A current measurement option of the test apparatus is connected to the external terminal 110 to measure the leak current of the selected bit line.
The current measurement of the test apparatus is relatively slow, taking an amount of time on the order of ms to 10 ms per an iteration of current measurement, whereby a test time generally on the order of 10 seconds is required for measuring all of the thousands of bit lines forming the memory array, greatly affecting the testing cost. It is often the case with test apparatuses that parallel testing is employed for reducing the effective test time in order to improve the throughput or reduce the testing cost. However, such parallel measurement requires the test apparatus to have an independent test resource for each device, thus resulting in an expensive test apparatus.
In order to avoid such a problem, the present inventors have proposed means for on-chip determination of the bit line leak current, wherein an external reference current is compared with the leak current of a selected bit line in terms of a voltage value obtained by integrating the current by means of a capacitor.
However, it has been found that the bit line leak determination has the following problem. With a memory of a virtual ground array arrangement using a source read method as shown in FIG. 21, the source bit line leak current is quite dependent on the potential applied to the source of the memory cell as shown in FIG. 23. In other words, the value of the source bit line leak current rapidly decreases as the source potential increases.
Therefore, where the conventional bit line leak determination is applied to a memory of a virtual ground array arrangement using a source read method, the leak current-integrated voltage is applied to the source of the memory cell, and the leak current value decreases according to the voltage, whereby it is difficult to determine the bit line leak current with high precision.
As described above, while a non-volatile memory made by a minute process requires a bit line leak current determination in order to realize high reliability, a determination by using a current measurement option of a test apparatus increases testing costs, such as the test time and the cost and the throughput of the test apparatus. Moreover, conventional on-chip bit line leak current determination means cannot determine a leak current with high precision.